Overview

With more than 20 years experience, we know the risks and challenges that your team have to confront, and our experienced engineers collaborate closely with your designer to accomplish project seamlessly without compromising performance and within target schedule. The business model of our SoC design service is adaptable, possible options including ASIC design, physical design, package/substrate design, custom layout etc. SiS production-proven design methodology is blended with in-house technologies, off-the-shelf EDA tools and engineering expertise greatly reduce your effect to success. This design methodology can be further configured to high performance design flow or low power design flow to fit distinct project characteristics.

Based upon project complexity, SiS adopts adequately either hierarchical or flatten physical implementation flow to realize IC optimal performance in competitive cycle time. We develops in-house technologies to reinforce design methodology, when off-the-shelf EDA tools cannot reach our standards or there is no available solution on the market at all. SiS patent pending in-house Clock Tree Generator(SCTG) can easily reduce clock skew of design by 30% with no extra clock buffer count. Our most advantageous in-house hold-time fixing technology is able to reach timing closure target with much lower delay-cell count.