- Pre-Condition
To simulate the environment conditions of the SMT process. Pop-corn, poor solderability, can be found on failed
parts.Improper molding material & process may induce this failure.
- HTST (High Temperature Storage Test)
To detect the effect of time and temperature under storage conditions, for thermally activated failure mechanisms of
solid state electronic devices.
- TCT (Temperature Cycle Test)
To enhance the mechanical stress induced by different thermal expansion coefficient of the materials. Delamination,
package crack, can be found on failed samples. Poor molding process, lead frame integrity & die attach process may induce
this failure.
- HAST (Highly Accelerated temperature & humidity Stress Test)
To verify the capability of packages to prevent the moisture penetration. This moisture penetration will make the metallization, PAD, wire corrosion and malfunction.
- ESD (Electro Static Discharge)
To determine the resistance of ESD, including HBM (human body mode), and CDM (charged device mode). The capability of ESD resistance is the intrinsic circuit characteristic of chip. The higher ESD resistance capability, the more chips will survive under worst application condition.
- Latch-up
To verify the circuit resistance to latch-up. Latch-up is also an intrinsic characteristic of a chip, & depends on the devices arrangement of circuit. It is important to reduce the EOS (electrical over stress) failure due to latch-up.
- HTOL (High Temperature Operation Life-time Test)
Using temperature and voltage to stress ICs to determine operation lifetime of ICs due to foundry process, & to evaluate lifetimes of ICs.