Low Power Solution
| Power reduction technique |
Leakage decrease |
Dynamic decrease |
Timing penalty |
Area penalty |
Flow Status |
| Gate count reduction |
Yes |
Yes |
No |
-10% |
Proven |
| Multi-Vt optimization |
Yes |
No |
No |
2-2% |
Proven |
| Clock gating |
No |
Yes |
No |
< 2% |
Proven |
| Multi-power domain design |
Yes |
Yes |
No |
2% |
Proven |
| Multi-supply voltage (MSV) |
Yes |
Yes |
No |
< 10% |
Proven |
| Power shut-off (PSO) Power gating |
Yes |
No |
Yes |
5-15% |
Flow ready |
| Dynamic voltage & frequency scaling |
Yes |
Yes |
No |
< 10% |
08/Q4 ready |
Designers need not only worry about the power reduction, but also other trade-off in terms of
area, timing and methodology. Methodology impact is what forces customers not to do advanced
techniques.
Above table gives a rough idea of the power reductions available from various techniques along with
the timing/area trade-offs and the potential methodology impact. In general, there is trade-off
between the amount of power reduction you can expect and the amount of work needed to apply the
techniques.
Challenge for the designers is to choose the most suitable power-management techniques that
deliver the target quality-of-silicon (QoS) while minimizing the cost and risk associated with
methodology changes. As an example, following techniques can be added to the traditional design
flow without fundamentally changing the way the tools work:
- Global concurrent optimization of timing, area, and power
- Leakage optimization methods, including multi-Vt synthesis
- Hierarchical clock gating
- Low-power clock tree synthesis
All of these techniques are useful, and the list could include a number of other techniques that
are well understood and involve minimal trade-offs for designers. Our recommendation is to certainly
consider these techniques as the first step towards adopting power-aware design methodologies.
Though easy to adopt, the power reduction from these techniques is limited and to achieve dramatic
reduction, you have to consider some advanced techniques.
Two of these techniques—multiple power domains and power-shut-off (PSO) methods—are worth a closer
look because they have become the focus for minimizing both active and leakage power in a broad range
of designs. Though, a number of design teams in the past used these techniques for power-critical
designs, the whole methodology was manually tedious and risky. Additionally, the design approach
resulted in sub-optimal power, area and timing trade-offs. However, over the last one year, EDA
tools have become available that automate the entire design flow and enable adoption of advanced
techniques with minimal methodology impact.
SiS Low power Implement Design methodology
SiS Low Power Verification Flow
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Chart on the left side illustrates the Encounter MSV flow and where Conformal Low Power fits
in it.In essence, Conformal LP is used through out the implementation flow from RTL to GDS for:
- Equivalence checking of low power designs
- Make sure no logic bugs are introduced by implementation tools
- Verify low power optimizations
- Check state retention mapping from RTL to gate
- MSV (multi-voltage islands) and power gating functional and Structural checks. Conformal LP supports
checks for logical as well as power aware physical netlists.
Equivalence checking for Low Power design
- Ensure low power optimizations do not introduce logical errors
- Verify gated clocks, gated signals, de-cloning of gated clocks
- Check State Retention mapping from RTL to gate
- Check corresponding presence of Isolation and level shifter during implementation
Power domain structural & functional checks
- Synthesized netlist checking (logical netlist)
- Verifies level shifter and isolation insertion
- Place and route netlist checking (power aware)
- Automatically derives the power domains
- Verifies power connectivity to low power cells
- Verifies level shifter and isolation logic insertion
- Verifies power control, isolation, and state retention function
- Transistor electrical verification
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