Design Methodology

Design flow in advanced process node is extremely difficult to reach high efficiency and predictability. None of EDA companies could completely provide satisfactory IC implementation and verification solution, though they all claim they do. After successfully producing hundreds of tapeout designs and millions of chips, SiS has developed a production-proven design methodology. The optimized flow includes in-house technologies, off-the-shelf EDA tools and engineering expertise, which not only save your effort to mass-production but also shorten your design cycle time. The design methodology can be further configured to high performance design flow or low power design flow to fit distinct project characteristics.

Timing closure is complicated by the effects of deep sub-micron in the form of signal integrity, power consumption, manufacturability and testability. Timing shall be considered in every major step of physical design; otherwise, frequent design iterations might severely impact project schedule. Because Off-the-shelf EDA tools do not always meet the requirements, SiS develops in-house technologies to reinforce physical design flow. Our patent pending in-house Clock Tree Generator(SCTG) can easily reduce clock skew of design by 30% with no extra clock buffer count, and our most advantageous in-house hold-time fixing technology is able to reach timing closure target with much lower delay-cell count. With the consideration of project complexity, SiS adopts adequately either hierarchical or flatten physical implementation flow to realize IC optimal performance in competitive cycle time.

The gap between true silicon characteristics and simulation & analysis results of design phase obviously cannot be neglected in the era of nanometer process technology. Timing closure, power integrity and manufacturability are not trivial issues, they all potentially influence project schedule, chip yield and product time-to-market. The purpose of signoff procedure is to ensure criteria of timing closure, power integrity and manufacturability are seriously followed before projects tapeout. SiS constantly correlates silicon characteristics with simulation & analysis results through continuously collaborate with customers, foundries and tool vendors to ensure the robustness of our signoff procedure.

Robust Signoff Procedure